Mr. Takyu ShinyaJapan
LINTEC Corporation
Current Position
2020 to presentAssistant General Manager
Academic Experiences
1987 - 1991The University of Electro-Communications
Past Professional Experiences
1991/04 - 2014/02TOSHIBA Corporation
2014/04 - LINTEC Corporation
Honors and Awards
Specialty & Expertise
Process Engineer, Planning, New business development
Others
Shinya Takyu developed the “Dicing Before Grinding” process; well known as DBG and contributed to the thin IC card chip and the 17 layers stack NAND Flash Memory package for mass production, He was the general chair of ICSJ2017 (IEEE CPMT Symposium Japan 2017), the Chair of IEEE EPS Japan (2023-2024), and now he is an IEEE EPS Board of Governors MEMBERS-AT-LARGE (2025-)

A Novel Process and Material for Hybrid Bonding of Thinner and Larger Chips Using Direct Transfer Bonding and Its Carrier Tape


TBA TBA International Symposium on Electronic Packaging Technology/TBA

​​​Reducing the power consumption of AI systems has become an urgent priority. Heterogeneous integration of memory, logic, and I/O circuits require technology for Hybrid Bonding (HB) of ultra-thin chips of arbitrary chip size using Chip on Wafer (CoW) bonding. Conventional CoW Process takes flowing process, a thinner chip is picked-up from dicing tape, hold the chip with transfer tool called collet, and bonding the chip on a wafer using Hybrid bonding. However, there are issues regarding CoW bonding processes, such as accuracy, throughput, and particles due to chip-level handling process. To solve these problems, Direct Transfer Bonding (DTB) technology has been developed. DTB is the process that a thinner chip is bonded with a carrier tape to a wafer pushing a bonding tool. In this method, the bonding tools and the thinner chip is never attached, so there are no particle issues, and accuracy and throughput are improved. Using this process and our carrier tapes, thinner and larger chips, specifically 50μm thick and 25 x 25 mm size are hybrid bonded successfully, also the Hybrid Bonding result of 10μm thick and 6 x 6 mm size chips are shown in my talk.​

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