Dr. Chia-Hong JanUSA
Intel (retired)
| 2017 to present | | IEEE Fellow |
| 2022 Feb - 2022 June | | Visiting Professor, Tsing-Hua University, Taiwan |
| 2016 - 2025 | | Intel Senior Fellow, Intel Corp. |
| 2022 - 2025 | | Technologist, Intel Corp. |
| 2016 - 2022 | | Director, System-on-Chip (SoC) and High Perf. Computing (HPC) Integration, Intel Corp. |
| 2010 - 2016 | | Fellow and Director of System-on-Chip (SoC), Intel Corp. |
| 2025 | | Outstanding Alumni Award, Dept. of Chem. Eng., National Taiwan University, Taipei, Taiwa |
| 2009 | | Intel Achievement Awards |
| 2008 | | Distinguished Achievement Award, College of Engineering at the Univ. of Wisconsin-Madison. |
1. Modern Semiconductor Manufacturing Process
2. Novel Material Technology Characterization, Integration and Application
3. System-on-Chip (SoC) and High Speed Computing Products Integration including CPU/Gfx, embedded DRAM, Chipset, FPGA and RF Products.
4. Experience to manage large technology development and production teams
Dr. Chia-Hong Jan is a former Intel executive. He had the position of Director of High Speed and Low Power Technology Integration, and Intel Senior Fellow, the highest technical rank at Intel (he was the first individual from Taiwan). The Institute of Electrical and Electronics Engineers (IEEE) has named Dr. Jan among its 2017 class of fellows. The honor recognizes Jan for his leadership in developing low power logic technologies for System-on-Chip (SoC).
In his 34 years tenure at Intel, he assumed various technical and leadership roles in 0.8µm, 0.55µm, 0.35µm, 0.25µm, 0.18µm, 0.13µm, 90nm, 65nm, 45nm, 32nm, 22nm, 14nm and 7nm advanced CMOS technologies. He started with the engineering group leader for rapid thermal processing and advanced silicon deposition engineering, working on the development of novel salicides, including Titanium, Cobalt and Nickel technology, advanced gate oxide processes, source and drain junction engineering, and epi SiGe technology for strained silicon. As the engineering manager of 90nm interconnect integration, his team was credited the first in industry to research, develop and ramp of low-k ILD materials for high-performance microprocessors. He was one of the co-inventors for the industry first SiGe strained technology. Jan was the program manager of 65nm low-power chipset process technology, and 45nm, 32nm, 22nm and 14nm SoC process technology for Intel® Atom™ processor–based low-power products, including micro-servers, tablets, smartphones, and chipsets, wireless, RF and FPGA products.
Jan has 162 U.S. Patents in the fields of semiconductor process, materials and integration.
Dr. Jan has published more than 50 technical papers. He has 7862 citations with H-index of 42 and I10 Index of 93. His paper of the development of industry first FinFET System-on-Chip (SoC), presented in IEEE IEDM’12, was selected as one of the 60 most influential papers in the IEDM conference history at IEDM 60th year anniversary (San Francisco, 2014). Two other Intel papers received the recognition were from Gordon Moore (Moore’s Law, 1975) and K. Mistry (1st High-k/Metal Gate, 2007)..
He received three Intel Achievement Awards (highest individual recognition at Intel). Dr. Jan is the recipient of the 2008 Distinguished Achievement Award from the College of Engineering at the University of Wisconsin-Madison.
Dr. Jan has been active in the EDS community, including IEDM committee, CSTIC Plenary (Shanghai, 2016), VLSI-TSA keynote (Taiwan, 2018), NATEA (San Jose, 2022) keynote, and EDL reviewer.
Jan holds a bachelor’s degree in Chemical Engineering and MBA from National Taiwan University, Taiwan. He also earned a master’s degree and Ph.D. in Materials Science from the University of Wisconsin-Madison.